1. Field of the Invention
The present invention relates to a semiconductor memory device and a driving method therefore, and relates to, for example, an FBC (Floating Body Cell) memory device storing therein information by accumulating carriers in floating bodies of respective field effect transistors.
2. Related Art
In recent years, there has been known an FBC memory device as a semiconductor memory device expected to replace a 1T (Transistor)-1C (Capacitor) DRAM. The FBC memory device is configured so that FETs (Field Effect Transistors) each including a floating body (hereinafter, also “body”) are formed on an SOI (Silicon On Insulator) substrate. The FBC memory device stores data “1” or “0” in each FET according to the number of majority carriers accumulated in the body of the FET.
In an FBC constituted by, for example, an nFET, it is defined that a state in which the number of holes accumulated in the body is large is data “1” and that a state in which the number of holes accumulated in the body is small is data “0”. Further, a memory cell storing therein data “0” is referred to as ““0” cell”, and a memory cell storing therein data “1” is referred to as ““1” cell”.
To retain data in each memory cell for a long time, it is necessary to set a potential of the body made of a p-type semiconductor lower than that of a source and a drain made of an n-type semiconductor. To retain data in the memory cell, a potential of a word line connected to the memory cell is set negative with respect to a potential 0 V of the source. Accordingly, a state of data “0” is deteriorated by causing holes to flow into the body of the “0” cell while the data is being held. To recover the state of the data “0” from the deterioration, it is necessary to execute refresh operation on all memory cells at certain time's intervals. The refresh operation is an operation for selecting all word lines in order and for restoring deteriorated storage states of all the memory cells to original states.
Even while an unselected “0” cell is in a data retention state, GIDL (Gate Inducted Drain Leakage) occurs to the unselected “0” cell if data “1” is written to a selected memory cell connected to a bit line connected to the unselected “0” cell. The GIDL is a phenomenon where holes flow into the body of the unselected “0” cell by band-to-band tunneling of the unselected “0” cell if a potential of a word line connected to the unselected “0” cell is negative and that of the bit line connected thereto is positive while the unselected “0” cell is in the data retention state. If a data retention period is long after data “0” is written to the unselected memory cell, i.e., the “0” cell, the number of holes flowing into the body of the unselected “0” cell is increased by writing of data “1” to the other memory cells connected to the bit line connected to the unselected “0” cell. As a result, the data “0” is deteriorated. This phenomenon is called “bit line “1” disturbance”.
When data “0” is written to a memory cell, the potential of the bit line connected to the memory cell, i.e., “0” cell is made negative. Due to this, a drain potential of a “1” cell connected to the same bit line is often made slightly lower than a body potential of the “1” cell. A weak forward bias is applied between the body and the drain of this “1” cell. This forward bias disturbs the “1” cell connected to the same BL as the cell to which data “0” is to be written. This phenomenon is called “bit line “0” disturbance”.
To deal with the bit line disturbance, it is necessary to perform the refresh operation on all the memory cells more frequently than a simple cycle required for retaining data.
The degree of the influence of the bit line disturbance varies according to the execution frequency of read or write operation. For example, if the read or write operation is executed more frequently from a certain refresh operation until a next refresh operation in a read or write mode, an unselected memory cell is greatly influenced by the bit line disturbance. Normally, an execution interval of the refresh operation is set according to memory cells greatly influenced by the bit line disturbance. Due to this, in the data retention period in which no read or write operation is performed, the execution frequency of the refresh operation is excess. As a result, power consumption is excessively high in the data retention period.